entity pipeline_alu_to_vrf is
  port(
    DATA_IN     : in std_logic_vector(3 downto 0);
    CLK_i       : in std_logic;
    DATA_OUT    : out std_logic_vector(3 downto 0)
  );
end pipeline_alu_to_vrf;

architecture structural of pipeline_alu_to_vrf is

  component reg_alu_to_vrf
    port(
      D_i     : in std_logic_vector(3 downto 0);
      CLK_i   : in std_logic;
      Q_o     : out std_logic_vector(3 downto 0) );
  end component;

begin
	U1 : reg_alu_to_vrf port map( 
		D_i   => DATA_IN,
		CLK_i => CLK_i,
		Q_o   => DATA_OUT );
end structural;
